1. Field of the Invention
The present invention relates generally to semiconductor devices and a method of manufacturing the same and, more particularly, to a semiconductor device having an MOS (Metal-Oxide-Semiconductor) transistor and a manufacturing method thereof.
2. Description of the Background Art
Conventionally, a semiconductor device including a P channel MOS transistor is known as one of semiconductor devices. FIG. 40 is a cross-sectional view showing a conventional semiconductor device including a P channel MOS transistor. Referring to FIG. 40, an isolation oxide film 102 is formed at a predetermined region on a main surface of an N type silicon substrate 101 for element isolation in the conventional semiconductor device. On an active region surrounded by isolation oxide film 102, P type source/drain regions 106a and 106b are formed spaced apart by a predetermined distance from each other to sandwich a channel region 110. On channel region 110, a gate electrode 104 is formed with a gate oxide film 103 posed therebetween. Sidewall oxide films 105 are formed at both sidewall portions of gate electrode 104.
A P channel MOS transistor is formed of P type source/drain regions 106a, 106b, gate oxide film 103 and gate electrode 104. Gate electrode 104 is formed of polycrystalline silicon including P type impurities such as boron (B) and has a thickness of about 2000 xc3x85.
FIGS. 41-46 are cross-sectional views showing a method of manufacturing the conventional semiconductor device shown in FIG. 40. Referring to FIGS. 40-46, a process of manufacturing the conventional semiconductor device will be described.
At first, as shown in FIG. 41, an isolation oxide film 102 is formed using LOCOS (LOCal Oxidation of Silicon) method at a predetermined region on the main surface of N type silicon substrate 101. A silicon oxide film (not shown) and a non-doped polycrystalline silicon film (not shown) having a thickness of about 2000 xc3x85 are formed all over the surface and then patterned, so that a gate oxide film 103 formed of the silicon oxide film and a gate electrode 104 formed of the non-doped polycrystalline silicon film are formed.
Next, as shown in FIG. 42, a resist 111 is formed using photolithography to cover a region except for gate electrode 104. Boron is ion-implanted into gate electrode 104 using resist 111 as a mask. After that resist 111 is removed. Next as shown in FIG. 43, heat treatment at a temperature in the range of about 800xc2x0 C. to 1000xc2x0 C. is carried out for thirty minutes to activate impurities (boron) ion-implanted into gate electrode 104.
As shown in FIG. 44, after a silicon oxide film (not shown) is formed all over the surface, a sidewall oxide film 105 is formed at both sidewall portions of gate electrode 104 by anisotropic etching.
As shown in FIG. 45, a resist 112 is formed on gate electrode 104 using photolithography. After that, as shown in FIG. 46, P type impurities such as boron are ion-implanted into silicon substrate 101 using resist 112, sidewall oxide film 105 and isolation oxide film 102 as a mask. Thus, P type ion-implanted regions 107a and 107b are formed.
After that, resist 112 is removed. Then, boron introduced into ion-implanted regions 107a and 107b is electrically activated by heat treatment at a temperature of 800xc2x0 C. for about thirty minutes. Thus, impurity diffusion regions (source/drain regions) 106a and 106b are formed as shown in FIG. 40. In this manner, a semiconductor device having a conventional P channel MOS transistor has been formed.
In the conventional semiconductor device described above, impurity is undesirably redistributed by the heat treatment in activating the impurity introduced into P type impurity implanted regions 107a and 107b shown in FIG. 46. More specifically, impurity introduced into P type impurity implanted regions 107a and 107b diffuses in all directions inside silicon substrate 101 by heat treatment. As a result, P type impurity diffusion regions (source/drain regions) 106a and 106b (see FIG. 40) which are larger than P type impurity implanted regions 107a and 107b are formed (see FIG. 46).
FIG. 47 is a cross-sectional view showing a problem of the conventional semiconductor device. Referring to FIG. 47, as the size of P type source/drain regions 106a and 106b becomes larger by impurity diffusion caused by heat treatment, channel length L is reduced. Thus, so called punch through phenomenon occurs in which current cannot be controlled by the gate voltage because a depletion layer in the vicinity of one of the source/drain regions 106a and 106b, for example, spreads to the other region thereof. This punch through phenomenon considerably appears when an element is miniaturized.
Another problem is that by heat treatment in activating P type impurity in a gate electrode 104, the P type impurity (boron) passes through a gate oxide film 103 to diffuse into a channel region 110. When the P type impurity in gate electrode 104 diffuses into channel region 110, there occurs a problem that threshold voltage the MOS transistor changes.
One object of the invention is to effectively prevent punch through phenomenon in a semiconductor device.
Another object is to effectively prevent the change of threshold voltage caused by diffusion of impurity in the gate electrode into the channel region in the semiconductor device.
Still another object is to effectively suppress the impurity diffusion caused by heat treatment in forming source/drain regions in a method of manufacturing a semiconductor device.
A further object of the invention is to effectively prevent the diffusion of impurities in the gate electrode into the channel region caused by heat treatment for activation thereof in the method of manufacturing the semiconductor device.
According to the first aspect of the present invention, a semiconductor device includes a semiconductor region of a first conductivity type having a main surface, a pair of source/drain regions of a second conductivity type having a predetermined junction depth formed spaced apart by a predetermined distance from each other to sandwich a channel region on the main surface of the semiconductor region, an implanted layer having depth equal to or greater than the junction depth of the source/drain regions, formed along the entire junction region of the source/drain regions and including a material selected from the group consisting of nitrogen, fluorine, argon, oxygen and carbon, and a gate electrode formed on the channel region with a gate insulation layer posed therebetween. Preferably, the implanted layer described above is formed to have depth greater than the junction depth of the source/drain regions and to cover the source/drain regions.
In the semiconductor device, since the implanted layer having the depth equal to or greater than the junction depth of the source/drain regions is formed along the entire junction region of the source/drain regions, impurity diffusion caused by heat treatment in forming the source/drain regions can be effectively prevented. Thus, unlike the conventional device, reduction of the channel length caused by the impurity diffusion is prevented, effectively reducing the punch through phenomenon. Note that if the implanted layer described above is formed to have the depth greater than the junction depth of source/drain regions and to cover the source/drain regions, the impurity diffusions caused by heat treatment in the formation of the source/drain regions is suppressed more effectively.
According to another aspect of the present invention, a semiconductor device includes a semiconductor region of a first conductivity type having a main surface, a pair of source/drain regions of a second conductivity type formed with a predetermined distance therebetween to sandwich a channel region on the main surface of the semiconductor device, and a gate electrode formed on the channel region with a gate insulation layer posed therebetween. The gate electrode includes impurity and an implanted layer including a material selected from the group consisting of nitrogen, fluorine, argon, oxygen and carbon near the surface at the side of the gate insulation layer.
In the semiconductor device, since the implanted layer is formed near the surface at the side of the gate insulation layer of the gate electrode including impurity, the impurity in the gate electrode is effectively prevented from passing through the gate insulation layer and diffusing into the channel region caused by heat treatment in activating the impurity in the gate electrode. Thus, change of the threshold voltage caused by the diffusion of the. impurity into the channel region is prevented.
According to still another aspect of the present invention, a method of manufacturing a semiconductor device includes the steps of forming a gate electrode at a predetermined region on the main surface of a semiconductor region of a first conductivity type with a gate insulation film posed therebetween, forming an implanted layer by ion-implanting a material selected from the group consisting of nitrogen, fluorine, argon, oxygen and carbon into the semiconductor region using the gate electrode as a mask with a first projected range, forming a pair of impurity regions of a second conductivity type by ion-implanting an impurity of a second conductivity type into the semiconductor region using the gate electrode as a mask with a second projected range which is smaller than the first projected range and effecting heat treatment.
In the method of manufacturing the semiconductor device, the implanted layer is formed by ion-implanting with a first projected range a material selected from the group consisting of nitrogen, fluorine, argon, oxygen and carbon into the semiconductor region of a first conductivity type, a pair of impurity regions of a first conductivity type are formed by ion-implanting impurity of a second conductivity type into the semiconductor region with a second projected range which is smaller than the first projected range, and then heat treatment is carried out, therefore diffusion of impurity in the impurity region is effectively suppressed by the implanted layer described above in heat treatment. Thus, unlike the prior art, reduction of channel length is prevented and as a result, punch through phenomenon is reduced effectively.
According to still another aspect of the present invention, a method of manufacturing a semiconductor device includes the steps of forming a gate electrode at a predetermined region on the main surface of a semiconductor region of a first conductivity type with a gate insulation layer posed therebetween, forming an impurity region having a predetermined depth from the upper surface of the gate electrode in the gate electrode by introducing impurity into the gate electrode, forming an implanted layer having a depth equal to or greater than that of the impurity region described above by ion-implanting a material selected from the group consisting of nitrogen, fluorine, argon, oxygen and carbon into the gate electrode and after that carrying out heat treatment.
In a method of manufacturing the semiconductor device, by ion-implanting a material selected from the group consisting of nitrogen, fluorine, argon, oxygen and carbon into a gate electrode including an impurity region having a predetermined depth, an implanted layer having a depth equal to or greater than that of the impurity region is formed and then heat treatment is carried out, therefore impurity in the impurity region is prevented from diffusing into the side of the gate insulation layer and from invading the channel region, owing to the implanted layer. Therefore, change of the threshold voltage is prevented. In the method of manufacturing the semiconductor device in accordance with the above aspects of the present invention, when nitrogen molecular ions (N2+) are used in introducing nitrogen, impurity diffusion can be suppressed as compared with the case when simple ions (N+) of nitrogen are used. More specifically, molecular ions (N2+) of nitrogen has twice the number of nitrogen elements and twice the mass number of the simple ion (N+) of nitrogen. Therefore, disorder in crystal property comes to be more likely in the region where molecular ions (N2+) of nitrogen are introduced. Accordingly, channeling phenomenon at the time of impurity ion implantation can be further suppressed, and diffusion of impurity during heat treatment can further be suppressed.
In a bipolar transistor in accordance with still another aspect of the present invention, the p type epitaxial growth layer includes boron and nitrogen. Therefore, diffusion of boron can be effectively prevented by nitrogen.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.